1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device, such as a non-volatile memory, in which two gate electrodes and an insulation layer interposed therebetween are used as a capacitor, and a method for manufacturing the same.
2. Description of the Related Art
In recent years, the demand for a technique for increasing the capacity and the operation speed of a semiconductor memory has become greater and greater. A nonvolatile memory, such as an EPROM or EEPROM, in which a structure consisting of first and second gate electrodes and an insulation layer interposed therebetween is used as a capacitor for storing data, is not an exception.
A conventional EPROM or EEPROM has a memory cell structure, in which one bit line contact is required for every two memory cells. Although development of the processing technique has allowed miniaturization of some elements of a memory cell, it is difficult, in general, to miniaturize a portion around a contact to the highest degree. This difficulty results from the fact that miniaturization in a lateral direction progresses in accordance with the development of photolithography techniques, whereas miniaturization in a vertical direction does not. In other words, it is difficult to reduce the depth of a contact hole or the aspect ratio. Rather, the depth of a contact hole becomes greater in accordance with the miniaturization in the lateral direction. More specifically, when a memory cell is reduced in size in the lateral .direction, the substrate thereof has great ruggedness. The disparity in the surface level of the substrate causes a disconnection of an Al wiring layer. Since a thick passivation layer is used in general to prevent the disconnection defect, the contact hole must be inevitably deep.
On the other hand, when the size of a contact hole is reduced, the contact resistance is increased and the disparity in the surface level of the substrate is great at the contact hole, resulting in a disconnection defect of an Al wiring layer. To reduce the influence of the surface level disparity of the substrate, the contact hole must be relatively large, so that a large amount of Al wiring material can be introduced into the hole.
As described above, miniaturization of a contact hole has not progressed, but miniaturization of a contact is indispensable in forming a fine memory cell. In addition, since a number of contact holes are required in a semiconductor device (one contact hole for every two cells), reduction in the manufacturing yield or a defect in a product tend to occur easily due to the contact holes.
To overcome the above problems, a memory cell, of a type which does not require a bit line contact, has been proposed (IDEM, pages 548 to 551, 1987). FIGS. 1A to 1C are schematic diagrams showing the steps of manufacturing a memory cell of this type. First, as shown in FIG. 1A, a first gate insulation layer 102 and a plurality of first gate electrodes (floating gate electrodes) 110 are formed on a p-type silicon substrate 101. Then, an n-type impurity is introduced, using the first gate electrodes 110 as masks, to an exposed portion of a surface region of the p-type silicon substrate 101, thereby forming an n.sup.+ diffusion region 109. Subsequently, as shown in FIG. 1B, a thick silicon oxide layer 108 is formed on the first gate insulation layer 102, and interposed between the first gate electrodes 110.
Thereafter, as shown in FIG. 1C, a second gate insulation layer 114 is formed on the first gate electrodes 110. A second gate electrode (control gate electrode) 115 is formed on the second gate insulation layer 114. The second gate insulation layer 114 is formed of a composite layer consisting of a polycrystalline silicon oxide layer 111, a silicon nitride layer 112 and a silicon oxide layer 113.
In a memory cell as shown in FIG. 1C, the bit line (n.sup.+ diffusion region 109) is formed just under the silicon oxide layer 108 and the second gate electrode (control gate electrode) 115 extends in a direction perpendicular to the bit line. Thus, a contact is formed in a region in which the bit line and the word line cross each other. Such a structure is called a cross-point type memory cell.
Since the above memory cell does not require a bit line contact which is difficult to miniaturize, the size thereof can be reduced to at least half that of a memory cell having a bit line contact. Further, the size of a memory cell can be reduced simply in accordance with the progress in miniaturization techniques such as photolithography. Thus, the requirement for a large capacity can be satisfied.
However, an increase in the capacity of a semiconductor memory device is accompanied by the following drawbacks: a considerable period of time is required for inspection before delivery; and the manufacturing cost is increased. Therefore, it is practically very difficult to reduce the size of a memory cell simply by means of fine processing techniques, while increasing the integration density of the memory cell. In addition, since there is a great demand for a high speed operation, as well as for an increase in capacity, not only miniaturization of the memory cell but also high performance and a high operation speed are indispensable. With regard to an EPROM or EEPROM as shown in FIG. 1C, in which the first and the second gate electrodes 110 and 115 and the insulation layer 114 interposed therebetween are used as a capacitor, it is known that the inspection time can be reduced by high speed writing and the operation speed can be increased by a high channel current, if the capacitance of the gate insulation layer 114 is increased.
However, although the conventional nonvolatile memory device as shown in FIG. 1C is advantageous in miniaturization of the device, the capacitance between the first and the second gate electrodes 110 and 115 cannot be as high as is required for a memory cell, since the area of a region between the first and the second gate electrodes 110 and 115 (a coupling area) is limited to only the portion Just above the channel of the memory cell. Also in a conventional memory cell of the type which requires a bit line contact, the region between first and second gate electrodes on an isolation oxide layer must be sufficiently large to secure a coupling area. This factor, in addition to the necessity for a bit line contact, limits the miniaturization of a memory cell. Jpn. Pat. Appln. Publication KOKAI No. 3-34578 discloses that the integration density of a memory cell which requires a bit line contact can be increased by increasing the coupling area.
The capacitance can also be increased by reducing the thickness of the second gate insulation layer 114. However, if the thickness is reduced, the gate breakdown voltage is lowered, resulting in reliability also being lowered. It is particularly notable in an EPROM or an EEPROM, since a high electrical field is applied to the gate insulation layer (102, 114) in data writing and erasing operations, that the gate breakdown voltage and the reliability are considerably lowered.
In general, a polycrystalline silicon is used as the material of the first gate electrode and a polycrystalline silicon oxide layer is used as the material of the second gate insulation layer. The polycrystalline silicon oxide layer has a low gate breakdown voltage and an inferior reliability. Therefore, to increase withstand voltage and improve reliability, a relatively thick polycrystalline silicon oxide layer is used as the second gate insulation layer. However, when the second gate insulation layer is thick, a desired capacitance cannot be obtained. When the capacitance of the second gate insulation layer is insufficient, considerable writing time is required, which increases operation cost. Further, since the transistor current is also insufficient, the operation speed cannot be increased satisfactorily. These problems are serious particularly in the structure shown in FIGS. 1A to 1C, since it has only a small coupling area.